1. Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for determining QoS parameters of processor generated memory requests.
2. Description of the Related Art
Memory latency is an important factor in determining the performance (e.g., instructions executed per second) of a processor. Over time, the operating frequencies of processors have increased dramatically, while the latency for access to dynamic random access memory (DRAM) in the typical system has not decreased as dramatically. Accordingly, the number of processor clocks required to access the external memory has increased.
Caches are utilized within processor architectures to combat the effects of memory latency on processor performance. Caches are relatively small, low latency memories incorporated into the processor or coupled nearby. The caches store recently used instructions and data under the assumption that the recently used information may be accessed by the processor again. Caches can also store prefetched data which is likely to be accessed by the processor in the near future. The caches thus reduce the effective memory latency experienced by a processor by providing frequently accessed information more rapidly than if the information had to be retrieved from the memory system in response to each access.
Caches are often included within an overall memory hierarchy having several different layers. These layers may include non-volatile storage (e.g., hard disk storage), random access memory (RAM), and one or more levels of cache memory. Processor-based systems may include a processor having one or more cores, wherein each of the one or more cores includes one or more cache memories. For example, many processors include at least one processor core having an instruction cache and a data cache, which may be at the top of the memory hierarchy. A cache memory at the top of the memory hierarchy may be referred to as a level one (L1) cache. Many processors also include a level two (L2) cache, which may be shared by the data and instruction caches of a processor core, and furthermore, may be shared by multiple processor cores in multi-core processors.
The memory hierarchy typically includes system memory, and within a system on chip (SoC), many processors and other components and devices may compete for memory access to a system memory via a memory controller. The memory controller may use quality of service (QoS) parameters to arbitrate among memory requests from processor cores and various other sources (e.g., graphics, display pipes, non-real-time agents). For example, in one embodiment, the processor cores can assign either low latency or best effort QoS parameters for memory requests originating from the processor cores. If all traffic is sent as low latency, the overall throughput of the system may be reduced. On the other hand, if all traffic is sent as best effort, this may result in an increase in latency for the processor cores' memory requests.